The present invention relates generally to manufacture of flash memory devices, and more particularly, to on-chip repair of a defective address of an array of core flash memory cells during testing of the array of core flash memory cells on-chip with minimized number of pins such that a maximized number of dies on a semiconductor wafer may be tested and repaired concurrently.
The xe2x80x9cDetailed Descriptionxe2x80x9d section is organized with the following sub-sections:
A. BIST(Built-in-Self-Test) System;
B. BIST(Built-in-Self-Test) Interface;
C. Back-End BIST(Built-in-Self-Test) State Machine;
D. On-Chip Repair of Defective Address of Core Flash Memory Cells;
E. Diagnostic Mode for Testing Functionality of BIST (Built-in-Self-Test) Back-End State Machine;
F. Address-Sequencer within BIST (Built-In-Self-Test) System;
G. Pattern Generator in BIST (Built-In-Self-Test) System;
H. On-Chip Erase Pulse Counter for Efficient Erase Verify BIST (Built-In-Self-Test) Mode; and
I. Generation of Margining Voltage On-Chip During Testing CAM Portion of Flash Memory Device.
The present invention relates to sub-section xe2x80x9cDxe2x80x9d entitled xe2x80x9cOn-Chip Repair of Defective Address of Core Flash Memory Cellsxe2x80x9d, with particular reference to FIGS. 20-32.
Referring to FIG. 1, a flash memory cell 100 of a flash memory device includes a tunnel dielectric structure 102 typically comprised of silicon dioxide (SiO2) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure 102 is disposed on a semiconductor substrate or a p-well 103. In addition, a floating gate structure 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure 102. A dielectric structure 106, typically comprised of silicon dioxide (SiO2), is disposed over the floating gate structure 104. A control gate structure 108, comprised of a conductive material, is disposed over the dielectric structure 106.
A drain bit line junction 110 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area 112 of the semiconductor substrate or p-well 103 toward a left sidewall of the floating gate structure 104 in FIG. 1. A source bit line junction 114 that is doped with the junction dopant is formed within the active device area 112 of the semiconductor substrate or p-well 106 toward a right sidewall of the floating gate structure 104 of FIG. 1.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or tunneled out of the floating gate structure 104. Such variation of the amount of charge carriers within the floating gate structure 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell 100 for example, a voltage of +9 Volts is applied on the control gate structure 108, a voltage of +5 Volts is applied on the drain bit line junction 110, and a voltage of 0 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are injected into the floating gate structure 104 to increase the threshold voltage of the flash memory cell 100 during programming of the flash memory cell 100.
Alternatively, during erasing of the flash memory cell 100, a voltage of xe2x88x929.5 Volts is applied on the control gate structure 108, the drain bit line is floated at junction 110, and a voltage of +4.5 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103 for example. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate structure 104 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100. Such an erase operation is referred to as an edge erase process by one of ordinary skill in the art of flash memory technology.
In an alternative channel erase process, a voltage of xe2x88x929.5 Volts is applied on the control gate structure 108 and a voltage of +9 Volts is applied on the semiconductor substrate or p-well 103 with the drain and source bit line junctions 110 and 114 floating. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate structure 104 to the substrate or p-well 103 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100.
FIG. 2 illustrates a circuit diagram representation of the flash memory cell 100 of FIG. 1 including a control gate terminal 150 coupled to the control gate structure 108, a drain terminal 152 coupled to the drain bit line junction 110, a source terminal 154 coupled to the source bit line junction 114, and a substrate or p-well terminal 156 coupled to the substrate or p-well 103. FIG. 3 illustrates an electrically erasable and programmable memory device 200 comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology. Referring to FIG. 3, the array of flash memory cells 200 includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell 100 of FIGS. 1 and 2. The array of flash memory cells 200 of FIG. 3 is illustrated with 2 columns and 2 rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells.
Further referring to FIG. 3, in the array of flash memory cells 200 comprising an electrically erasable and programmable memory device, the control gate terminals of all, flash memory cells in a row of the array are coupled together to form a respective word line for that row. In FIG. 3, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line 202, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line 204.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In FIG. 3, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line 206, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line 208. Further referring to FIG. 3, the source terminal of all flash memory cells of the array 200 are coupled together to a source voltage VSS, and the substrate or p-well terminal of all flash memory cells of the array 200 are coupled together to a substrate voltage VSUB.
Referring to FIG. 4, a flash memory device comprised of an array of flash memory cells as illustrated in FIG. 3 for example is fabricated on a semiconductor die of a semiconductor wafer 220. A plurality of semiconductor dies are manufactured on the semiconductor wafer 220. Each square area on the semiconductor wafer 220 of FIG. 4 represents one semiconductor die. More numerous semiconductor dies are typically fabricated on a semiconductor wafer than shown in FIG. 4 for clarity of illustration. Each semiconductor die of FIG. 4 has a respective flash memory device comprised of an array of core flash memory cells.
During manufacture of the flash memory devices on the semiconductor wafer 220, each flash memory device on a semiconductor die is tested for proper functionality, as known to one of ordinary skill in the art of flash memory device manufacture. Referring to FIG. 5, an example semiconductor die 222 has a flash memory device comprised of an array of core flash memory cells 224. Referring to FIGS. 3 and 5, during testing of the flash memory device on the semiconductor die 222, an external test system applies bias voltages on the array of core flash memory cells 224 via contact pads 226 of the semiconductor die 222 for testing the array of core flash memory cells 224.
Referring to FIGS. 3 and 5, patterns of programming and erasing voltages are applied on the array of core flash memory cells 224 by the external test system via the contact pads 226 according to a plurality of flash memory test modes. For example, the array of core flash memory cells 224 are programmed and erased in an alternating checker-board pattern in one test mode. Alternatively, the flash memory cells located in the diagonal of the array of core flash memory cells 224 are programmed in another test mode. Then, a read operation is performed on the array of core flash memory cells by the external test system for each test mode via the contact pads 226 to determine that the array of core flash memory cells 224 are properly programmed and erased. Such a plurality of flash memory test modes and such an external test system for testing the proper functionality of the array of core flash memory cells are known to one of ordinary skill in the art of flash memory device manufacture. An example of such an external test system is the model V3300, available from Agilent Technologies, Inc., headquartered in Palo Alto, Calif.
In addition, a mechanism is desired for minimizing the number of pins used for repairing a defective addresses of core flash memory cells such that a maximized number of semiconductor die may be tested concurrently with an external test system having a limited total number of pins, to increase throughput during manufacture of flash memory devices.
Accordingly, in a general aspect of the present invention, repairing of the defective addresses of flash memory cells by replacement with redundancy elements of flash memory cells is performed on-chip to minimize the use of pins from the external test system and for an efficient repair mechanism.
In one embodiment of the present invention, in an apparatus and method for repairing a defective address of an array of flash memory cells fabricated on a semiconductor die, components for repairing the defective addresses of flash memory cells by replacement with redundancy elements of flash memory cells are also fabricated on the semiconductor die. During testing of the array of core flash memory cells, a repair routine is invoked when the defective address of flash memory cells fails a current BIST (built-in-self-test) mode. A FAILREP logic, fabricated on the semiconductor die, determines whether any redundancy element of flash memory cells is available for replacing the defective address of flash memory cells to enter a HANG state for the current BIST (built-in-self-test) mode if no redundancy element of flash memory cells is available. In addition, the FAILREP logic also determines whether the defective address of flash memory cells has been previously repaired to enter the HANG state for the current BIST (built-in-self-test) mode if the defective address of flash memory cells has been previously repaired.
A repair controller, fabricated on the semiconductor die, controls voltage sources fabricated on the semiconductor die to program a respective set of CAM (content addressable memory) flash memory cells for replacing the defective address of flash memory cells with a corresponding redundancy element of flash memory cells when the FAILREP logic determines that the corresponding redundancy element of flash memory cells is available and that the defective address of flash memory cells has not been previously repaired. A repair matching unit, fabricated on the semiconductor die, verifies that each flash memory cell of the respective set of CAM flash memory cells for replacing the defective address of flash memory cells has been properly programmed. The repair controller controls the voltage sources to re-juice by re-applying programming voltages on the respective set of CAM flash memory cells corresponding to the defective address of flash memory cells when the repair matching unit determines that each flash memory cell of the respective set of CAM flash memory cells for replacing the defective address of flash memory cells has not been properly programmed.
The repair matching unit and the repair controller repeat verifying that each flash memory cell of the respective set of CAM flash memory cells has been programmed and re-applying programming voltages on the respective set of CAM flash memory cells corresponding to the defective address of flash memory cells with an increment of PULSE_COUNT until each flash memory cell of the respective set of CAM flash memory cells for replacing the defective address of flash memory cells has been programmed with the PULSE_COUNT being less than Max_PC (maximum pulse count), or until PULSE_COUNT reaches the Max_PC with any of the respective set of CAM flash memory cells for replacing the defective address of flash memory cells not being programmed to enter the HANG state for the current BIST (built-in-self-test) mode.
In this manner, the repair of a defective address of flash memory cells during testing of the array of core flash memory cells by programming the CAM (content addressable memory) to replace the defective address of flash memory cells with the redundancy element of flash memory cells is performed on-chip. Thus, pins from the external test system are not used for programming the CAM (content addressable memory) to replace the defective address of flash memory cells with the redundancy element of flash memory cells. With use of such minimized number of pins from the external test system, a higher number of semiconductor dies may be tested concurrently by the external test system having a limited total number of pins, to maximize throughput during manufacture of flash memory devices.
In addition, because such repair by programming the CAM flash memory cells is performed on-chip, the speed of performing such a repair mechanism is not limited by the capacity of the external test system. Thus, such an on-chip repair mechanism may be more efficient.